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Data Registers: 0x01 OUT_X_MSB, 0x02 OUT_X_LSB, 0x03 OUT_Y_MSB, 0x04 OUT_Y_LSB, 0x05 OUT_Z_MSB, 0x06
OUT_Z_LSB
These registers contain the X-axis, Y-axis, and Z-axis14-bit output sample data expressed as 2's complement numbers.
Note: The sample data output registers store the current sample data if the FIFO data output register driver is disabled, but if
the FIFO data output register driver is enabled (F_MODE > 00) the sample data output registers point to the head of the FIFO
buffer (Register 0x01 X_MSB) which contains the previous 32 X, Y, and Z data samples. Data Registers F_MODE = 00
0x01: OUT_X_MSB: X_MSB Register (Read Only)
Bit 7
XD13
Bit 6
XD12
Bit 5
XD11
Bit 4
XD10
Bit 3
XD9
Bit 2
XD8
Bit 1
XD7
Bit 0
XD6
0x02: OUT_X_LSB: X_LSB Register (Read Only)
Bit 7
XD5
Bit 6
XD4
Bit 5
XD3
Bit 4
XD2
Bit 3
XD1
Bit 2
XD0
Bit 1
0
Bit 0
0
0x03: OUT_Y_MSB: Y_MSB Register (Read Only)
Bit 7
YD13
Bit 6
YD12
Bit 5
YD11
Bit 4
YD10
Bit 3
YD9
Bit 2
YD8
Bit 1
YD7
Bit 0
YD6
0x04: OUT_Y_LSB: Y_LSB Register (Read Only)
Bit 7
YD5
Bit 6
YD4
Bit 5
YD3
Bit 4
YD2
Bit 3
YD1
Bit 2
YD0
Bit 1
0
Bit 0
0
0x05: OUT_Z_MSB: Z_MSB Register (Read Only)
Bit 7
ZD13
Bit 6
ZD12
Bit 5
ZD11
Bit 4
ZD10
Bit 3
ZD9
Bit 2
ZD8
Bit 1
ZD7
Bit 0
ZD6
0x06: OUT_Z_LSB: Z_LSB Register (Read Only)
Bit 7
ZD5
Bit 6
ZD4
Bit 5
ZD3
Bit 4
ZD2
Bit 3
ZD1
Bit 2
ZD0
Bit 1
0
Bit 0
0
OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored in the auto-
incrementing address range of 0x01 to 0x06 to reduce reading the status followed by 14-bit axis data to 7 bytes. If the F_READ
bit is set (0x2A bit 1), auto increment will skip over LSB registers. This will shorten the data acquisition from
7 bytes to 4 bytes. The LSB registers can only be read immediately following the read access of the corresponding MSB register.
A random read access to the LSB registers is not possible. Reading the MSB register and then the LSB register in sequence
ensures that both bytes (LSB and MSB) belong to the same data sample, even if a new data sample arrives between reading the
MSB and the LSB byte.
6.2
32 Sample FIFO
The following registers are used to configure the FIFO. For more information on the FIFO please refer to AN4073 .
F_MODE > 0 0x00: F_STATUS FIFO Status Register
When F_MODE > 0, Register 0x00 becomes the FIFO Status Register which is used to retrieve information about the FIFO.
This register has a flag for the overflow and watermark. It also has a counter that can be read to obtain the number of samples
stored in the buffer when the FIFO is enabled.
0x00: F_STATUS: FIFO STATUS Register (Read Only)
Bit 7
F_OVF
Bit 6
F_WMRK_FLAG
Bit 5
F_CNT5
Bit 4
F_CNT4
Bit 3
F_CNT3
Bit 2
F_CNT2
Bit 1
F_CNT1
Bit 0
F_CNT0
MMA8451Q
Sensors
22
Freescale Semiconductor, Inc.
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